The present invention relates to a technique applicable effectively to a semiconductor device, e.g., a vertical high breakdown voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) which permits ON resistance to be made small and permits reduction of a device area.
A vertical high breakdown voltage MOSFET, i.e., a power MOSFET, has various characteristics such as being superior in frequency characteristic, high in switching speed and capable of being driven at a low power. For this reason the MOSFET in question is used in various industrial fields.
For increasing output, the power MOSFET adopts a structure wherein a large number of unit MOSFETs (cells) are arrayed over a main surface of a semiconductor substrate. Examples of cell shapes include quadrangular, hexagonal, and circular shapes. In the case of circular or hexagonal cells, there is adopted a so-called triangular array in which three adjacent cells are centered respectively on vertices of a triangle. In the case of quadrangular cells, there is adopted a so-called quadrangular array in which four adjacent cells are centered respectively on vertices of a quadrangle. Also in the case of quadrangular cells it is possible to adopt a triangular array.
In the case of circular or hexagonal cells arranged in a triangular array, if depletion layers are created by increasing voltage gradually, the potential relaxed by the depletion layers at the center of the triangle in the triangular array becomes higher than the potential related by depletion layers at the center of a quadrangle in a quadrangular array, with consequent occurrence of avalanche breakdown, so that the breakdown voltage cannot be set large in comparison with the quadrangular array. In the present situation, a maximum breakdown voltage of 1500V or so is possible in the case of quadrangular cells in a quadrangular array, but in the case of circular cells in a triangular array, an upper limit is 200V, and in the case of hexagonal cells in a triangular array, an upper limit is 600V or so.
In each unit MOSFET, a source contact hole is quadrangular, hexagonal, or circular in shape, and a source region is formed along a peripheral edge of the source contact hole and inside and outside the hole. Therefore, a planar pattern of the source region is a quadrangular frame pattern in the case of a quadrangular cell, is a hexagonal frame pattern in the case of a hexagonal cell, or is a ring-like pattern in the case of a circular cell.
In forming base and source regions, diffusion is performed using a gate electrode-including portion as a mask for impurity diffusion to determine the depth (spreading length in the planar direction) of the base region and that of the source region. In the case of a quadrangular cell, the spread of impurity at each corner portion becomes radial, so that the impurity concentration at each corner becomes lower than that in impurity diffusion at each side of a quadrangle and hence the threshold voltage becomes lower. Consequently, in the case where a steep current is applied, there occurs a current concentration to a portion where the threshold voltage is low, with eventual breakage of the device. For avoiding this inconvenience there has been proposed a structure in which a source region is not disposed at each corner. That is, there is adopted a rectangular or convex shape wherein a source region is allowed to cross each side of a quadrangle (see, for example, Patent Literatures 1 and 2).
[Patent Literature 1]
Japanese Unexamined Patent Publication
No. Sho 63 (1988)-289871 (page 3, FIGS. 1, 2 and 4)
[Patent Literature 2]
U.S. Pat. No. 4,641,162 (column 6, FIG. 4)